Senior or Principal Verification Engineer

Senior or Principal Verification Engineer

Job Title: Senior or Principal Verification Engineer
Contract Type: Permanent
Location: Reading
Salary: Competitive
Reference: ST68
Contact Name: Shannen Talbot
Job Published: July 17, 2019 09:55

Job Description

A leading semiconductor company located in Reading, as part of their ongoing expansion, is looking to strengthen their verification team, by recruiting a Senior or Principal Verification Engineer.  

If you believe yourself to be self-motivated, with 5-10 years’ experience in the industry and relish the opportunity of working on a diverse range of projects that will both challenge and develop your verification skills then keep reading!

As the Senior or Principal Verification Engineer, you will be joining a privately owned and funded IC design house with a consistent record of financial growth and technical excellence. Working for a range of customers from start-ups to blue-chip companies, and project portfolios from module design to multi-million gate System-on-Chip.

You will have a good understanding of different methodologies, but particularly SystemVerilog and UVM. Faced with a new project, you will have the ability to quickly assimilate the verification challenge and help define an effective (and pragmatic) verification strategy and gain the support of the end-customer for the chosen approach.

As you rapidly build your verification skills through engagement on a broad range of projects you will have the opportunity to take on the role of verification lead, with responsibility for architecting the test environment and driving the other team members to deliver the agreed solution.

Ideally, you will be familiar with both Mentor Questa and Cadence Incisive tools.

As the Senior or Principal Verification Engineer, your responsibilities will include:

  • Verification specialist working on customer and internal projects – sometimes as the verification lead.
  • Provide high-class verification support to a wide range of projects using a range of advanced verification techniques including constrained random, coverage driven, assertion-based and formal methods.
  • As a verification lead you would also be responsible for the development of a comprehensive verification strategy and plan, along with the architecting and development of the complete test environment.
  • Active participation in the verification community to drive the introduction of new and effective techniques within our business – to help solve the verification challenges faced by our customers.

Essential skill and experience needed:

  • Degree qualified in Electronics, Physics or Computer Science
  • 5-10 years experience in industry working on a variety of verification projects
  • Extensive knowledge of verification methodologies particularly UVM and SystemVerilog
  • Strong experience in the specification and implementation of verification infrastructures, test benches, models, assertions and functional tests in Verilog and SystemVerilog
  • Familiarity with constrained random verification methodologies, code coverage analysis and running regression tests
  • Strong VHDL/Verilog RTL

Excellentworking environment, flexible working, matched contribution pension scheme, subsidised private healthcare scheme, life assurance, and share options scheme.

If you are interested in applying for this role, please email Shannen at

If you find this opportunity interesting but perhaps not for you, please do share it with others who may be interested.