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ASIC / FPGA Design & Verification Engineer

Job description

Design & Verification Engineer – ASIC / FPGA | 6 Month Contract
Inside of IR35
Rate: £600 - £800 pd
Location: Cambridge
Working Environment: Hybrid (2/3 days on-site)
The company is one of the most prestigious tech firms in the world and a global powerhouse in the semiconductor industry, operating at the bleeding edge of technology and redefining the way we interact with our devices through the creation of advanced semiconductor and software designs.
You will be joining their Hardware Platform team as an experience Design & Verification engineer, working on the translation of FPGA architecture specifications into RTL designs with accompanying verification environments. These designs will then be incorporated into SoC and reference designs before being tested and delivered to their prototyping teams.
Key Requirements:
  • Experienced in the RTL design using Verilog and/or System Verilog for ASIC and/or FPGA’s.
  • Experienced in RTL verification using System Verilog, including coding SVA checks.
  • Strong understanding of FPGA device architecture.
  • Experience of programming in C within a UNIX environment, and scripting languages.
Desired, but not essential:
  • Experience of RTL designs for SoC.
  • Experience of working with SV UVM test benches and using UVM verification IP’s.
  • Experience of using verification techniques such as cover-properties, coverage groups.
  • Xilinx FPGA technology.