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IC Verification Engineer

Job description

A fantastic opportunity has arisen to work for a very impressive client based locally in Cambridge. Due to growth and success, my client is looking to recruit a high-calibre IC Verification Engineer, with a background in low power/ UPF (unified power format).

What makes this opportunity unique is the challenge and variety that will involve verification of both IPs and SoCs, covering all aspects of the verification flow from verification planning and development of environments through to testcase writing, gathering coverage and maintaining regression suites.

As the IC Verification Engineer you will have access to a wide range of tools from simulation and formal methods through to FPGAs. With our client’s philosophy of continuous improvement, you are encouraged to propose enhancements to flow and contribute to the advancement of current verification methodology.

To be successful, you will possess the following skills/ experience: 

  • SystemVerilog/UVM
  • Verification planning and closure
  • Assertions
  • Formal verification
  • Low power/UPF
  • Python

Experience of network/ display interfaces is advantageous.

Location: Cambridge (accessible from Cambridge North station) 
Salary: Competitive  
Benefits: Bonus, 25 days annual leave, Life Assurance, Private Healthcare, Pension scheme, and much more

If you find this opportunity interesting but perhaps not for you, please do share it with others who may be interested. 

If you are interested in applying for this role, please email Shannen at